/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:36:57 2011
//--
//-- Source file: dma_ch_fifo.v
//---------------------------------------------------------


  
module dma_axi64_core0_ch_fifo (CLK,WR,RD,WR_ADDR,RD_ADDR,DIN,BSEL,DOUT);

   
   input                      CLK;
   
   input               WR;
   input               RD;
   input [5-3-1:0] WR_ADDR;
   input [5-3-1:0] RD_ADDR;
   input [64-1:0]      DIN;
   input [8-1:0]      BSEL;
   output [64-1:0]     DOUT;
   
   
   reg [64-1:0]           Mem [4-1:0];
   wire [64-1:0]       BitSEL;
   wire [64-1:0]       DIN_BitSEL;
   reg [64-1:0]           DOUT;
   
     assign               BitSEL = {{8{BSEL[7]}} , {8{BSEL[6]}} , {8{BSEL[5]}} , {8{BSEL[4]}} , {8{BSEL[3]}} , {8{BSEL[2]}} , {8{BSEL[1]}} , {8{BSEL[0]}}};

   
   assign               DIN_BitSEL = (Mem[WR_ADDR] & ~BitSEL) | (DIN & BitSEL);
   
   always @(posedge CLK)
     if (WR)
       Mem[WR_ADDR] <= #1 DIN_BitSEL;

   
   always @(posedge CLK)
     if (RD)
       DOUT <= #1 Mem[RD_ADDR];

   
endmodule


